Abstract The complexity of hardware design methodologies represents a significant difficulty for non hardware focused scientists working on CNN-based applications. An emerging generation of Electronic System Level (ESL) timberland earthkeepers boots design tools is been developed, which allow software-hardware codesign timberland sale uk and partitioning of complex algorithms from High Level Language (HLL) descriptions.
These tools, together with High Performance Reconfigurable Computer (HPRC) systems consisting of standard microprocessors coupled with timberland sale boots application specific FPGA chips, provide a new timberland kids boots approach for rapid emulation and acceleration of CNN-based applications. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, is analyzed. A sequential CNN architecture, suitable for FPGA implementation,… proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers.
Results for a typical timberland boat shoes uk edge detection algorithm shown that, with a minimum development time, a 10x acceleration, when compared timberland sale code to the software emulation, can be obtained.